VHDL Language Basic

This course is aimed at all those who work in the field of electronics (Hardware, Firmware, and Software MiddleWare designers) who want to master the versatility and potential of FPGA programmable devices. The course consists of two days entirely dedicated to the introduction to the VHDL language.

To participate in the course, knowledge of the fundamental principles of programming using high-level languages is required.

Course program

Day 1:

1.  Introduction
   • Introduction to FPGAs
   • Different types of FPGAs
   • Architecture
   • Usage
2. Modeling Hardware
3. Introduction to Tools
   • Simulator (Modelsim)
   • Environment of prog. (Xilinx ISE)
4. VHDL
   • Main characteristics
   • Entities and architectures
   • Typing
   • Signals
   • Variables
   • Std_logic library
   • Processes
   • Types of programming:
     • Dataflow
     • Structural
     • Behavioral
     • Mixed
   • Examples
5. Synthesizable VHDL
   • Simulation Vs Synthesis
   • Examples of synthesis
6. Finite State Machines (FSM)
7. Programming at the RTL level

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Day 2:

1. VHDL
   • Libraries
   • Package
2. Xilinx ISE
   • Usage
   • IP library
   • Details on BlockRAM and FIFO
3. Testbench
   • Validation of the project
4. Using the Logic Analyzer
   • Integrated Logic Analyzer
   • Virtual IO
5. Examples
6. Clock domains
   • Comm. Between diff. clock domains
   • Metastability
   • Digital Clock Manager
   • PLL
7. HardIP of FPGAs
   • Multipliers
   • DSP block
   • Others
8. Examples
   • FIR pipelined filter
   • Sequential FIR filter
9. RocketIO and synchronous serial
   • Usage
   • Aurora
   • Channel bonding
10. Interfacing external peripherals
    • ADC / DAC